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Home > News > Optimization of a buffer layer for cubic silicon carbide growth on silicon substrates
Optimization of a buffer layer for cubic silicon carbide growth on silicon substrates
A procedure for the optimization of a 3C–SiC buffer layer for the deposition of 3C–SiC/(001) Si is described. After a standard carbonization at 1125 °C, SiH4 and C3H8 were added to the gas phase while the temperature was raised from 1125 °C to the growth temperature of 1380 °C with a controlled temperature ramp to grow a thin SiC layer. The quality and the crystallinity of the buffer layer and the presence of voids at the SiC/Si interface are related to the gas flow and to the heating ramp rate. In order to improve the buffer quality the SiH4 and C3H8 flows were changed during the heating ramp. On the optimized buffer no voids were detected and a high-quality 1.5 μm 3C–SiC was grown to demonstrate the effectiveness of the described buffer.
Highlights
• A procedure for the optimization of a 3C–SiC buffer layer for the deposition of 3C–SiC/(001) Si is presented.
• Buffer layer quality and voids at interface depends on the gas flow and heating ramp rate. Lower ramp heating rate yield the best results.
• On the optimized buffer very few density of voids were detected.
• High-quality 1.5 μm 3C–SiC was grown to demonstrate the effectiveness of the described buffer.
 
Fig. 1. (a) Wiener-filtered HR-TEM 110 cross section image of a carbonized silicon substrate and (b) corresponding Fast Fourier Transform showing its reciprocal lattice. In (a) the distance between the inclined planes in the top 2 nm is 0.255 nm, which is the lattice spacing of the SiC (111) planes. Six of such planes are located between the two black segments. The {111} lattice spacing of Si is 0.314 nm, as indicated in white. The diffraction pattern shown in (b), where the weak {111} Bragg spots of SiC are indicated by arrows, confirms the formation of a carbonized layer.

Source: Journal of Crystal Growth

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