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PERC solar cells on below 100 μm thick silicon ribbon wafers


Despite falling raw silicon feedstock prices, the development of thin silicon wafers is worthwhile for reducing total production costs of solar cells. Its advantage is not only saving energy-intensive silicon material: thin wafers have lower requirements on the carrier lifetime since reasonable cell results can already be reached with small effective diffusion lengths. The Ribbon on Sacrificial Template (RST) technology, which is a direct wafer casting method, meets these demands. In this study we apply a passivated emitter and rear solar cell (PERC) process, which was developed for defect-rich multicrystalline silicon materials at the University of Konstanz, on below 100 μm thin RST wafers. An independently confirmed efficiency of up to 16.0% are demonstrated on a 2x2 cm² solar cell. Hence, the mass of Si needed per Wp of this cell is below 1.5 g/Wp. In contrast, a comparable standard multicrystalline cell exhibits 4.3 g/Wp with the inclusion of kerf-loss. Loss analysis in terms of illuminated Lock-In Thermography and Laser Beam Induced Current show RST specific defects. A direct relationship between silicon carbide particle density and fill factor is presented. 
1. Introduction 
For reducing material costs in silicon solar cell production, the wafer thickness is one of the relevant parameters. About 40% of the total module costs are caused by the silicon wafer including feedstock, ingot casting and wafering [1]. However, the production of wafers with a thickness below 100 μm faces a huge challenge. In addition, large material losses occur due to slicing wafers from ingots. A solution to these problems can be addressed to the Ribbon on Sacrificial Template (RST) process [2]. The RST process belongs to the family of silicon ribbon technologies and represents a method of fast and kerf-loss free wafer casting. Hereby, molten silicon is directly crystallized on a carbon based substrate, which is removed by a high-temperature burn-off step afterwards. This method is successfully applied by the company Solarforce (France), where wafer thicknesses down to 50 μm can be achieved. In addition, a high wafer throughput rate is possible due the pull rate of ca. 5 cm/min, which is about two to four times faster than the speed of the comparable EFG (Edge-defined Film-fed Growth) process [3]. Determination of the solar cell efficiency potential and the characterization of RST material are of immanent relevance for future development and competitiveness of the RST technology. In this study we apply a PERC solar cell process developed for defect-rich mc-Si materials [4] on below 100 μm thin RST wafers.
2. Material and cell process
2.1. RST casting process and material quality
The RST casting process is presented in Fig. 1. A carbon-based carrier is pulled through molten silicon which directly crystallizes on the substrate surfaces. The substrate is removed by a high-temperature burn-off step afterwards. The vertical pull direction results in the growth of elongated grains with a varying width in the range of 1 to 1.5 mm. The relatively high pull rate achieved in the process, originates from the mechanical and thermal properties of the carbon substrate which prevents buckling and favors the formation of an extended growth interface [2]. The thickness of the ribbon wafers can be varied from 50 μm up to 200 μm by changing casting parameters like pull rate and melt temperature. For the cells presented in this work, the wafers had an initial thickness of 90-100 μm. The PL image of a RST wafer after a P-gettering step and SiNx:H firing is shown in Fig. 1 on the right side. The lifetime is calibrated by a quasi-steady-state photo conductance (QSSPC) measurement [5].
The elongated grain structure in pulling direction is clearly visible. Grains of increased charge carrier lifetimes alternate with low lifetime regions. At a minority carrier density of n=1014 cm-3 an average  lifetime of about eff=6 μs is observed. This corresponds to an effective diffusion length of up to Leff=130 μs extracted by a fit to the internal quantum efficiency (IQE) curves of comparable RST cells according to Basore [6].
2.2. PERC cell process
Besides the RST wafers a mc reference was processed for monitoring the solar cell process. In the photolithography based PERC cell process four 2x2 cm² lab type solar cells can be obtained from one 5x5 cm² wafer. The process is depicted in Fig. 2. The front side (FS) is textured with a plasma etching tool resulting in a sponge like surface. A anti-reflection coating and passivation of the front side is realized with a silicon nitride layer (SiNx:H) done by plasma-enhanced chemical vapour deposition (PECVD). On the rear side (RS) the back contact is realized with laser fired contacts (LFC) [7]. The contact sintering of the front contacts and an enhanced hydrogen passivation is done by a microwave  induced remote hydrogen plasma (MIRHP) step. A double anti-reflection coating (DARC) using MgF2 is applied to the best cells only. More details about the cell process and efficiencies reached on several other silicon materials can be found in [4].
3. Cell results
3.1. Electrical characterization
IV results received from the best cells with a single layer anti-reflection coating (SARC) on plasma textured surface can be seen in Tab. 1. The IV measurements are carried out under AM 1.5G illumination and at 25°C. The cells are divided in groups where cells processed on RST wafers with a base resistivity of b~1 cm are indicated by group 1. Correspondingly, group 2 consists of b~2 cm RST cells and group 3 is the reference group with multicrystalline silicon wafers of b~1 cm (standard mc wafer thickness 180 μm). With a SARC a highest efficiency of 15.5% on RST wafers is demonstrated. This is the highest efficiency obtained so far on this kind of wafer material.
Applying a DARC normally leads to an increase of 0.4 to 0.6%abs in efficiency [8]. Results thus obtained by applying a DARC with MgF2 on the best RST cell are also given in Tab. 1. The 
independently confirmed efficiency of 16.0% is an increase of around 2%abs compared to previous record values [8]. The IV-parameters of all cells with SARC are summarized in Fig. 3. The cells of both RST groups have comparable median open circuit voltage of Voc,1 = 598 mV and Voc,2 = 599 mV (Voc,3 = 623 mV). The lower base resistivity leads to a higher maximal value of Voc,max = 611 mV. This is a reasonable value for typically defect-rich ribbon wafers and corresponds to a good crystal quality. On the other hand, the median short circuit current density of group 1 of jsc,1 =30.1 mA/cm2 suffers from the lower base resistivity compared to group 2 with jsc,2 =33.6 mA/cm2 (jsc,3 =35.2 mA/cm2). The fill factor seems also to be influenced by b. Whereas group 2 exhibits a median fill factor of FF2=72.1%, group 1 just reaches a median of FF1=68.2% (FF3=77.2%). In total this finally leads to median efficiencies of 1=12.2% and 2=14.4% ( 3=16.8%). 
3.2. Loss analysis 
The RST cells show reduced performance compared to the mc references. To fathom the loss mechanisms different measurements described in the following are carried out on some cells. With reflectance and spatially resolved laser beam induced current (LBIC) measurements (50 μm steps) IQE maps can be computed. To ensure that the whole bulk is taken into account an excitation wavelength of the laser of Laser=980 nm is chosen. This corresponds to a penetration depth of dp~100 μm which is in the order of the cell thickness. 
With the determined reflectivity of the cells of typically 20% at 980 nm IQE maps of a mc reference and three different RST cells with decreasing fill factor are shown in Fig. 4. It is clearly obvious that a loss in fill factor corresponds to a lower IQE signal at long wavelengths. An indication for loss of fill factor gives the illuminated Lock-In Thermography (iLIT). Fig. 5 depicts the iLIT maps of the same cells which are shown in Fig. 4, with a Lock-In frequency of 60 Hz. The spots are a sign for shunts and strong recombination active regions. This is one reason for the restriction of the fill factor of RST cells. The shunts are presumably caused by SiC structures which occur at the carbon substrate and wafer interface. In addition, the shunts lead to lower parallel resistances and higher j02 values. 
4. Discussion 
The dependence of the fill factor to the SiC particle density is shown in Fig. 6. A loss in fill factor can apparently be linked to a higher particle density. For comparison, a comparable correlation by Hari Rao et al. [9] on EFG material is plotted in the same diagram. 
The influence of the SiC particles on RST wafers seems not to be as strong as on EFG wafers. The strength of the influence is given by the gradient determined by a linear fit to the measurement data given in Fig. 6. The gradient yields a change of about RST = -3.26 0.5 %cm2
 on RST wafers. This is nearly half as much as the influence on EFG with EFG = -5.66 0.5 %cm2
. The formation of SiC particles is supposed to be the source of shunts. Shunt areas which are indicated by iLIT measurements are identified as foreign particles in the optical microscope. Fig. 6 shows some typical particle structures on the wafer surface. Local reactions of the carbon based substrate with the molten silicon during wafer casting leads to infiltration of silicon into the carbon carrier and thus to the formation of SiC dentrites. The exact identification of the defects with scanning electron microscopy und electron dispersive x-ray 
spectroscopy at the specific areas is part of future work. 
5. Conclusion 
By applying a PERC process on RST wafers solar cells were processed to basically characterize the material and to gain insight into the material quality. RST wafers with a thickness below 100 μm and b~2 cm achieved a maximum independently confirmed efficiency of 16.0%. Loss analysis with LBIC and iLIT revealed shunts as a main reason for limitation of fill factor and efficiency. With optical microscopy it could be shown that the shunts originate from SiC particles at the wafer surface. These particles are formed by the reaction of molten silicon with the carbon based substrate during wafer casting. Further work will focus on the solar cell processing and characterization of RST wafers produced with optimized casting conditions and hence reduced SiC particle densities. 
[1] Powell DM, Winkler MT, Choi HJ, Simmons CB, Berney Needleman D, Buonassisi T. Crystalline silicon photovoltaics: a cost analysis framework for determining technology pathways to reach baseload electricity costs. Energy Environ Sci 2012;5:5874-83. 
[2] Belouet C. Growth of silicon ribbons by the RAD process. J Cryst Growth 1987;82:110-6. 
[3] Bell RO, Kalejs JP. Growth of silicon sheets for photovoltaic applications. J Mater Res 1998;13:2732 9. 
[4] Junge J, Ebser J, Graf S, Terheiden B, Seren S, Hahn G et al. Evaluating the efficiency limits of low cost mc Si materials using advanced solar cell processes. Proc 25th EU PVSEC, Valencia, Spain 2010:1722-6. 
[5] Sinton RA, Cuevas A. Contactless determination of current voltage characteristics and minority carrier lifetimes in semiconductors from quasi steady state photoconductance data. Appl Phys Lett 1996;69(17):2510-2. 
[6] Basore PA. Numerical Modeling of textured silicon solar cells using PC1D. IEEE Trans ED 1990;37(2):337-43 
[7] Schneiderlöchner E, Preu R, Lüdemann R, Glunz S. Laser-fired rear contacts for crystalline silicon solar cells. Prog Photovolt 2002; 34, p. 29-34. 
[8] Keller P, Hess U, Seren S, Junge J, de Moro F, Hahn G. Over 14% Efficiency on RST-Ribbon Solar Cells. Proc. 27th EU PVSEC, Frankfurt, Germany 2012, p. 2053-7. 
[9] Hari Rao CV, Bates HE, Ravi KV. Electrical effects of SiC inclusions in EFG silicon ribbon solar cells. J Appl Phys1976;47(6):2614-9
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