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Home > News > Growth and surface analysis of SiO2 on 4H-SiC for MOS devices
Growth and surface analysis of SiO2 on 4H-SiC for MOS devices

 

 

The growth effects of SiO2 on the C-face and Si-face 4H-SiC substrates are thoroughly investigated by AFM analysis.

The growth mechanism of different species involved in the growth process of SiO2by wet thermal oxide is now proposed by adopting two body classical projectile scattering. This mechanism drives to determine growth of secondary phases such as α-CH nano-islands in the grown SiO2 layer.

The effect of HF etchings on the SiO2 layers grown by both techniques and on both the C-face and Si-face substrates are legitimately studied.

The thicknesses of the layers determined by AFM and ellipsometry techniques are widely promulgated.

The MOS capacitors are made on the S-face 4H-SiC wafers by wet oxidation and sputtering processes, which are studied by capacitance versus voltage (CV) technique. From CV measurements, the density of trap states with variation of trap level for MOS devices is estimated.

 


Abstract

The SiO2 layers have been grown onto C-face and Si-face 4H-SiC substrates by two different techniques such as wet thermal oxidize process and sputtering. The deposition recipes of these techniques are carefully optimized by trails and error method. The growth effects of SiO2 on the C-face and Si-face 4H-SiC substrates are thoroughly investigated by AFM analysis. The growth mechanism of different species involved in the growth process of SiO2 by wet thermal oxide is now proposed by adopting two body classical projectile scattering. This mechanism drives to determine growth of secondary phases such as α-CH nano-islands in the grown SiO2 layer. The effect of HF etchings on the SiO2 layers grown by both techniques and on both the C-face and Si-face substrates are legitimately studied. The thicknesses of the layers determined by AFM and ellipsometry techniques are widely promulgated. The MOS capacitors are made on the Si-face 4H-SiC wafers by wet oxidation and sputtering processes, which are studied by capacitance versus voltage (CV) technique. From CV measurements, the density of trap states with variation of trap level for MOS devices is estimated.

Keywords

  • Silicon oxide
  • 4H SiC
  • Atomic force microscopy
  • Wet thermal process
  • Interface trap density states
  • Capacitance voltage

Source:Sciencedirect


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